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XR18W750
WIRELESS UART CONTROLLER
REV. 1.0.0
1.0 PRODUCT DESCRIPTION
The XR18W750 is a Digital Baseband with a two-wire I 2 C interface to the XR18W753 RF transceiver to
complete Exar ’s Wireless UART chipset solution. An external I 2 C EEPROM is required to store Exar ’s
proprietary firmware and Wireless UART chipset parameters.
The XR18W750 is functionally, as well as architecturally, divided into the following blocks and modules:
? 8051 Microprocessor
? Enhanced UART
? AES Engine
? I 2 C Interface
1.1
8051 Microprocessor
The embedded 8051 microprocessor is compatible with the industry standard 803x/805x microprocessors
using a standard 8051 instruction set. The embedded 8051 microprocessor has a high-speed architecture that
takes four clocks per instruction cycle, eliminates wasted bus cycles and improves instruction execution time
on average by 2.5X over the standard 8051. The embedded 8051 microprocessor has a 32KB system
memory for loading the firmware from an external I 2 C EEPROM and for data processing. The firmware is
loaded from the external I 2 C EEPROM upon power on or reset. A 16MHz clock is required for correct
operation of the 8051 microprocessor. (This same 16MHz clock is also used by the enhanced UART in the
XR18W750.) For the firmware for communicating with the XR18W753 RF Transceiver, send an e-mail to
uarttechsupport@exar.com.
1.2
Enhanced UART
A CPU or serial port can communicate with the XR18W750 via the enhanced 64 byte FIFO UART. The
XR18W750 can communicate with an external CPU when the parallel mode is enabled (S/P# connected to
GND) or it can communicate directly with another serial port when the serial mode is enabled (S/P# connected
to VCC). The enhanced UART has a register set that is compatible to the industry standard 16550, but with
additional features such as Auto RTS/CTS Hardware Flow Control, Programmable TX and RX FIFO Trigger
Levels, and a Programmable Fractional Baud Rate Generator.
1.2.1
Parallel Mode
When the parallel mode is enabled, an external CPU can communicate with the enhanced UART via either the
Intel bus (CS#, IOR#, IOW#, INT) or Motorola bus (CS#, R/W#, IRQ#) interface. Any data that is written to the
TX FIFO of the enhance UART will be transmitted serially to UART of the 8051 microprocessor, where it is
processed and sent via the I 2 C interface to the RF Transceiver.
1.2.2
Serial Mode
When the serial mode is enabled, an external serial port can communicate with the enhanced UART via RS-
232, RS-422, or RS-485. The data that is received in the RX FIFO of the enhanced UART will be read out via
the parallel bus by the 8051 microprocessor, where it is processed and appropriate actions are taken. There
are two modes of operation in the serial mode: Command Mode and Data Mode. In the command mode, the
enhanced UART can be configured via AT commands.
1.3
AES Engine
The internal 128-bit AES engine guarantees that the data is transmitted securely from one Wireless UART
chipset to another Wireless UART chipset with the same AES security key. This prevents other wireless
devices on the same frequency to listen in on the Wireless UART chipset unless it knows the 128-bit AES
security key.
1.4
I 2 C Interface
The I 2 C interface on the XR18W750 operates in the I 2 C master mode. The I 2 C interface is a two-wire serial
interface consisting of a serial data line (SDA) and serial clock line (SCL). The maximum I 2 C clock frequency
is 400 kHz. The XR18W750 loads the firmware from the EEPROM and can communicate with an RF
Transceiver like the XR18W753 via the I 2 C interface.
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